The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2000

Filed:

Jun. 08, 1999
Applicant:
Inventors:

Naoshi Adachi, Ogi-gun, JP;

Takehiro Hisatomi, Nishimatuura-gun, JP;

Masakazu Sano, Saga, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
F27D / ; B05C / ; C30B / ;
U.S. Cl.
CPC ...
117204 ; 206710 ; 206711 ; 206712 ; 206832 ; 206833 ; 211 4118 ; 118500 ; 118724 ; 118728 ; 432253 ;
Abstract

This invention anneals a vertical stack of two or more groups of unseparated wafers, with approximately 10 wafers in each group. The invention makes it possible to anneal more wafers in a single annealing operation under a variety of conditions, including: oxygen outer diffusion annealing to form a denuded zone; annealing to control bulk micro defects and provide intrinsic gettering functions; annealing to enhance gate oxide integrity by eliminating crystal-originated particles from the wafer surface and internal grown-in or as-grown defects; and suppression of dislocation and slip in elevated temperature environments.


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