Method and apparatus for monitoring bus transactions based on cycle type

Abstract

Memory controller logic for concurrently obtaining memory access locality information by cycle type for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. The monitoring logic further includes a programmable cycle control register and comparison logic to condition the page access counters for specific memory cycle types, such as coherency cycles, reads, writes, copyback cache cycles, etc. Whenever the processing node generates a transaction requiring access to a memory address within system memory which matches the cycle type specified in the cycle control register, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns by cycle type is created which can be used to optimize memory and process assignments in the computer system.