The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2000
Filed:
Nov. 10, 1998
Fu-Liang Yang, Tainan, TW;
Erik S Jeng, Hsinchu, TW;
Bih-Tiao Lin, Ping Tung, TW;
I-Ping Lee, Taouan, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell; forming a first conductive layer in said plurality of first contact holes and on said first dielectric layer; patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously; forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections; and patterning and etching said second dielectric layer and said second conductive layer to form a charge storage means and a plurality of contact plugs.