The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2000
Filed:
Jan. 05, 1999
Freidoon Mehrad, Plano, TX (US);
Sarma S Gunturi, Richardson, TX (US);
Cetin Kaya, Dallas, TX (US);
Kyle A Picone, Austin, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of fabricating a semiconductor device having a memory array (9) that includes a source line (24) is provided. The method of forming the source line (24) may include providing a semiconductor substrate (52) having a source region (60) separated from a drain region (62) by a channel region (64). An isolation structure (70) may be formed in the semiconductor substrate (52). The isolation structure (70) may cross the source region (60), the drain region (62), and the channel region (64) of the semiconductor substrate (52). An isolation dielectric material (78) may be formed within the isolation structure (70). A continuous stack structure (50) may be formed outwardly from the channel region (64) of the semiconductor substrate (52) and the isolation structure (70). A first photomask (100) may be formed outwardly from the continuous stack structure (50) and the semiconductor substrate (52). The first photomask (100) may expose a strip region (102) of the semiconductor substrate (52) and the isolation structure (70). The isolation dielectric material (78) may be removed from the exposed portion the isolation structure (70) to expose the semiconductor substrate (52). A dopant may be implanted into the exposed semiconductor substrate (52) to form the source line (24) in the semiconductor device.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile