The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2000

Filed:

Sep. 05, 1997
Applicant:
Inventors:

Hideki Matsumura, Kanazawa, JP;

Akira Izumi, Nomi-gun, JP;

Atsushi Masuda, Nomi-gun, JP;

Yasunobu Nashimoto, Tokyo, JP;

Yosuke Miyoshi, Tokyo, JP;

Shuji Nomura, Tachikawa, JP;

Kazuo Sakurai, Fuchu, JP;

Shouichi Aoshima, Inagi, JP;

Assignees:

Hideki Matsumra, Kanazawa, JP;

NEC Corporation, Tokyo, JP;

ANELVA Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438788 ; 438792 ; 438795 ; 438798 ;
Abstract

This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.


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