The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2000
Filed:
Sep. 30, 1998
David W Daniel, Divide, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of the integrated circuit. The buried layer implant is the final implanting step during fabrication of the integrated circuit structure. In another technique, fabricating the integrated circuit structure includes performing multiple sequential processes some of which are performed at elevated temperatures above about 500.degree. C. A buried layer is implanted beneath a surface of the integrated circuit. After implanting the buried layer, the substrate is subjected to a fabrication process at an elevated temperature above about 800.degree. C. only once. Propagation of defects, such as in-the-range defects or ion enhanced stacking faults, from the buried layer to other device layers during the fabrication process is reduced.