The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2000
Filed:
Dec. 09, 1997
Frederick R Gruner, Palo Alto, CA (US);
Ralph Portillo, Mountain View, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A logic array includes an AND plane, a first OR plane, and a second OR plane. The AND plane is adapted to receive a plurality of logic array inputs and provide a plurality of minterms. Each minterm represents a logical combination of a subset of the plurality of logic array inputs. The first OR plane is adapted to receive the minterms and provide a plurality of intermediate outputs. Each intermediate output represents a logical combination of a subset of the minterms. The second OR plane is adapted to receive the intermediate outputs and provide a plurality of logic array outputs. Each logic array output represents a logical combination of a subset of the intermediate outputs. A method for programming a logic array includes providing a plurality of minterms. A plurality of subsets of the minterms are logically combined to define a plurality of intermediate outputs. A plurality of subsets of the intermediate outputs are logically combined to define a plurality of logic array outputs.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile