The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2000
Filed:
Oct. 29, 1996
Angelo Magri', Belpasso, IT;
Ferruccio Frisina, Sant'Agata Li Battiati, IT;
Giuseppe Ferla, Catania, IT;
SGS-Thomson Microelectronics, S.r.l., Agrate Brianza, IT;
Consorzio per la Ricerca Sulla Microelettronica nel Mezzogiorno, Catania, IT;
Abstract
A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.