The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2000

Filed:

Jun. 03, 1998
Applicant:
Inventors:

Douglas Ray Sparks, Kokomo, IN (US);

Larry Lee Jordan, Kokomo, IN (US);

Ruth Ellen Beni, Carmel, IN (US);

Anthony Alan Duffer, Kokomo, IN (US);

Shing Yeh, Kokomo, IN (US);

Assignee:

Delphi Technologies, Inc., Troy, MI (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
2281231 ; 2281246 ; 228174 ; 228208 ;
Abstract

A method by which semiconductor wafers (10, 12) can be solder bonded to form a semiconductor device, such as a sensor with a micromachined structure (14). The method entails forming a solderable ring (18) on the mating surface of a device wafer (10), such that the solderable ring (18) circumscribes the micromachine (14) on the wafer (10). A solderable layer (20, 26, 28) is formed on a capping wafer (12), such that at least the mating surface (24) of the capping wafer (12) is entirely covered by the solderable layer (20, 26, 28). The solderable layer (20, 26, 28) can be formed by etching the mating surface (24) of the capping wafer (12) to form a recess (16) circumscribed by the mating surface (24), and then forming the solderable layer (26) to cover the mating surface (24) and the recess (16) of the capping wafer (12). Alternatively, the solderable layer (28) can be formed by depositing a solderable material to cover the entire lower surface of the capping wafer (12), patterning the resulting solderable layer (28) to form an etch mask on the capping wafer (12), and then to form the recess (16), such that the solderable layer (28) covers the mating surface (24) but not the surfaces of the recess (16).


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