Test circuitry for determining the defect density of a semiconductor

Abstract

A test structure according to the present invention provides a technique for determining defects as a function of metal layers. The technique is implemented by dividing the test structure into individual test blocks that correspond to certain metal layers. In the disclosed embodiment, for example, a test structure formed by a semiconductor process utilizing three layers of interconnect metal includes three distinct test blocks having similar or identical underlying test logic. In a first test block, the underlying test logic is predominantly connected by the first metal layer. In a second test block, the underlying test logic is predominantly connected by the second metal layer. In a third test block, the underlying test logic is primarily connected by the third metal layer. During the testing stage, test patterns are applied to each test block and the results are tabulated. Faults detected in a test block are allocated to the metal layer(s) corresponding to the predominant metal routing layer of the test block. Because the test logic is the same, faults due to the underlying test logic or transistors comprising the test logic can be discounted. In this manner, the test results of the different test blocks can be compared and problems with a specific metal or via layer are readily identified. In one embodiment of the invention, the test structure is located on a production die. In another embodiment, the test structure is located on a test die.