The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2000
Filed:
Aug. 21, 1998
Thomas Schulz, Munich, DE;
Thomas Aeugle, Munich, DE;
Wolfgang Roesner, Munich, DE;
Lothar Risch, Neubiberg, DE;
Siemens Aktiengesellschaft, Munich, DE;
Abstract
In the circuit arrangement two of the four vertical transistors are complementary to the remaining two transistors. Two of the transistors are respectively arranged at the same level. For this purpose, layer structures (St1, St2, St3, St4) are structured that respectively have at least a channel layer and a source/drain region of one of the transistors. All the layer structures (St1, St2, St3, St4) can be produced from a layer sequence with only four layers. In order to avoid leakage currents due to a parasitic bipolar transistor, the layer structures (St1, St2, St3, St4) can be realized very thinly, using spacer-type masks. Electrical connections between parts of the four transistors can take place via layers of the layer sequence. The contacting to the output voltage terminal can take place via a step that is formed by two layers of the layer sequence.