The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2000

Filed:

Sep. 05, 1997
Applicant:
Inventors:

Minh Van Ngo, Union City, CA (US);

Darin A Chan, Campbell, CA (US);

Sey-Ping Sun, Austin, TX (US);

Terri Kitson, San Jose, CA (US);

John Caffall, Fremont, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438778 ;
Abstract

An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiO.sub.x N.sub.y stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiO.sub.x N.sub.y stop layer within the CVD reactor chamber. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.


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