Planarization on an embedded dynamic random access memory

Abstract

A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.