The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2000
Filed:
Apr. 09, 1999
Katsumi Ochiai, Gyoda, JP;
Toshiaki Misono, Gyoda, JP;
Advantest Corp., Tokyo, JP;
Abstract
A timing generator for a semiconductor test system having an interleave architecture with no interleave jitters. The timing generator includes a plurality of timing data generators arranged in a parallel fashion and provided with a first clock signal in which each of the timing data generator produces a coarse timing signal and a delay time data based on timing data provided by a test program, a multiplexer provided with a second clock signal having a frequency higher than the first clock signal for receiving the coarse timing signals and delay data in parallel and produces selected one of coarse timing signal and the delay data in series, and a variable delay circuit which receives the coarse timing signal and the delay data from the multiplexer for providing a delay time defined by the delay data to the coarse timing signal.