Method and apparatus for enabling redundant memory

Abstract

A method and apparatus for selectively enabling and disabling access to prime and redundant memory elements based on an address to a prime memory element is described. By receiving a prime element address and comparing it to program defective addresses, a signal indicating a correspondence between addresses is provided when a match occurs. The indication may be used as a select signal to a multiplexer for selecting between inputs. Moreover, an indication of a correspondence between addresses may be latched for temporary storage. The signal indicating whether or not a match has been found is provided to an override circuit, which selectively determines which enable signals are to be active and which are to be inactive. This allows for access to a prime element, a redundant element instead of a prime element, a redundant element instead of a prime and/or a redundant element, and so on. Additionally, a timing control enable signal may be employed to control timing of providing an enable signal. The memory having enable circuitry may be employed in any of a variety of memories and systems.