Delay circuit and delay chain circuit for measurement of the

Abstract

A delay circuit is provided to dynamic random-access memory (DRAM) for use to assist the measurement of the DRAM charge/discharge period, which allows the DRAM charge/discharge period to be more precisely measured. In measurement, a plurality of such delay circuits are chained together to allow the charge/discharge period measurement to be performed in a collective manner on all the DRAM cells in the delay chain circuit, which can be then used to determine the charge/discharge period of each DRAM cell. When the charge or discharge process on the DRAM cell in the current stage is completed, the DRAM-cell delay circuit of the current stage will likewise generate an output voltage of a certain logic state to trigger the next stage to undergo a charge/discharge process. Furthermore, a large-current output driving circuit is coupled to the last stage in the delay chain circuit to allow an increased output driving capability.