The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2000
Filed:
Apr. 30, 1998
Ken Takeuchi, Tokyo, JP;
Tomoharu Tanaka, Yokohama, JP;
Kabushiki Kaishi Toshiba, Kawasaki, JP;
Abstract
A memory cell array includes first and second memory cell groups which are simultaneously selected at the time of erasing. A first bit line is connected to the first memory cell group and a second bit line is connected to the second memory cell group. The first and second bit lines are commonly connected to a data circuit having a latch circuit. First data read from the first memory cell group at the time of erase verify read for the first memory cell group is input to the data circuit and second data read from the second memory cell group at the time of erase verify read for the second memory cell group is input to the data circuit. The data circuit latches data indicating that the erasing operation is completed into the latch circuit when both of the first and second data items indicate that the erasing states of the memory cells are sufficient and latches data indicating that the erasing operation is effected again into the latch circuit when at least one of the first and second data items indicates that the erasing state of the memory cell is insufficient.