The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2000

Filed:

Nov. 21, 1996
Applicant:
Inventors:

Tomoyoshi Tajiri, Tokyo, JP;

Takao Kusano, Tokyo, JP;

Kazuya Ohkawa, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257 88 ; 257 91 ; 257 93 ; 257 94 ; 257 96 ; 257 97 ; 257 99 ;
Abstract

A light emitting diode array includes a light emitting area formed on a semiconductor substrate, a diffusion prevention layer formed on the semiconductor substrate, and an insulating layer formed on the diffusion prevention layer. The diffusion prevention layer has a lower edge and the insulating layer has a level drop at this lower edge. An interconnection conductor extends on the insulating layer and is in ohmic contact with the light emitting region through holes in the insulating layer and the diffusion prevention layer. The interconnection conductor has a stepped portion at the level drop of the insulating layer, the stepped portion being located in a wide-width segment of the interconnection conductor. A method for forming such a light emitting diode array includes the steps of providing a semiconductor substrate, forming a light emitting region on the substrate, forming a diffusion prevention layer on the substrate surrounding the light emitting region, forming in insulating layer on the diffusion prevention layer, covering the light emitting region and the insulating layer with a conductive layer, forming a mask layer on a predetermined portion of the conductive layer, the mask layer having a wide-width segment located on the stepped portion, and selectively forming the interconnection conductor by etching the conductive layer using the mask layer. Several embodiments of both the method and the array are disclosed.


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