The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2000
Filed:
Nov. 21, 1996
Mieko Suzuki, Tokyo, JP;
Tetsuya Homma, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A fabrication method of a semiconductor device is provided, which enables the formation of a conductive plug in an opening of an interlevel dielectric layer without arising any void. After a first wiring layer is formed on a first interlevel electric layer, a second interlevel dielectric layer is formed on the first interlevel dielectric layer to cover the first wiring layer. A first opening is formed in the second interlevel dielectric layer. A first conductive layer is formed on or over the second interlevel dielectric layer to cover the first opening. A first protection layer is formed on the first conductive layer to cover a first depressed part of the first conductive layer. The first protection layer having a first buried part on the first depressed part. The first protection layer and the first conductive layer are polished by a CMP process until the second interlevel dielectric layer is exposed, thereby selectively leaving the first depressed part within the first opening. The first depressed part left within the first opening constitutes a first conductor plug for electrically interconnecting the first wiring layer with a second wiring layer formed to be contacted with the fist conductor plug.