The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2000

Filed:

Mar. 11, 1999
Applicant:
Inventors:

Yen-Lin Ding, Hsinchu, TW;

Gary Hong, Hsin-Chu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438264 ; 438257 ; 438594 ;
Abstract

A method for manufacturing a flash memory. A substrate having a patterned pad oxide layer formed thereon and a patterned mask layer on the pad oxide layer is provided. A doped region is formed in the substrate exposed by the patterned mask layer and the pad oxide layer. A spacer is formed on the sidewall of the patterned mask layer and the pad oxide layer to cover a portion of the doped region. A trench is formed in the substrate exposed by the mask layer and the spacer. An insulating layer is formed to fill the trench, wherein the insulating layer leveled with a top surface of the patterned mask layer. The patterned mask layer and the spacer are removed to respectively expose the patterned oxide layer and the portion of the doped region. A self-aligned tunnel oxide layer is formed on the portion of the doped region. A patterned first conductive layer is formed over the substrate to expose portions of the patterned pad oxide layer above the substrate excluding the doped region. A self-aligned doped region is formed in the substrate under the patterned pad oxide layer exposed by the patterned first conductive layer. A dielectric layer is formed on the patterned first conductive layer and the self-aligned doped region. A patterned second conductive layer is formed over the substrate.


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