Multiple internal phase-locked loops for synchronization of chipset

Abstract

Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit. The following steps are performed for each selected output pin coupled to provide a synchronized clock signal at the end of a propagation trace: a) determining an electrical length of the propagation trace; and b) providing a feedback trace from the output pin to a feedback pin of the corresponding PLL, wherein the feedback trace is a same electrical length as the propagation trace. A divided-by-n reference clock signal is then provided to at least one of the PLLs, wherein n is not equal to 1.