The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 2000
Filed:
Dec. 11, 1997
David Bang, Palo Alto, CA (US);
Qi Xiang, Santa Clara, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An ultra-thin dielectric film is subject to a dynamic electrical bias. During a first phase, the ultra-thin dielectric film is under a high field bias generated by the application of a high voltage. The duration of the high electrical stress is dependent on the intrinsic properties of the ultra-thin dielectric material. In a second phase, the ultra-thin dielectric film is subjected to an operating field bias generated by the application of an operating voltage. The change in the field bias exposes the dielectric to a similar dynamic stress that microelectronic devices ordinarily experience. At the operating field stage, a gate current is measured and compared to a predetermined range. Once the gate current exceeds that range the test concludes. Otherwise, the test cycles between the above-mentioned phases for a predetermined number of iterations based on prior experimental correlation. In a destructive testing mode, the process is continuous and does not conclude until the gate current exceeds a predetermined range. The ultra-thin dielectric gate current may also be measured as the ultra-thin dielectric is heated so that the transport properties or reliability of the ultra-thin dielectric is more clearly understood.