Method and device for multi-level programming of a memory cell

Abstract

A method and device for programming multiple levels of voltage states in a memory cell. A program and verify memory cell device includes a memory cell coupled with at least one dummy cell, the devices sharing common drain, gate, and source nodes. The threshold voltage of each dummy cell is set to a target threshold level for programming the memory cell. A stair-step sequence of pulses is used to program and verify the memory cell. A constant current source can also be coupled between the source node and the ground. The programming steps for this device include applying a high voltage to the drain and gate nodes, and coupling the source to level while starting the program pulse, then establishing a constant current at the source to pull it from high to level, and then applying program and verify pulses at the memory cell gate. A self convergence memory cell device includes the parallel connected memory and dummy cells above, but with at least one current sensing device coupled between the dummy cell and the drain. The programming steps for this device include applying a high voltage to the drain and gate nodes, and coupling the source to level while starting the program pulse, then establishing a constant current at the source to pull it from high to level, and then using the current sensing device to pull down the drain when a certain dummy cell current is reached upon subsequent application of programming pulses.