Growth enhancement of hemispherical grain silicon on a doped polysilicon

Abstract

A process for creating a storage node electrode for a DRAM capacitor structure, featuring increased surface area accomplished using an HSG silicon layer as the top layer for the storage node electrode, has been developed. The process features the use of a composite buffer layer of undoped and lightly doped amorphous silicon layers, located overlying a heavily doped amorphous silicon layer, and then followed by the deposition of HSG silicon seeds. A first anneal cycle then allows formation of an undoped HSG silicon layer to be realized on the underlying heavily doped amorphous silicon layer, via consumption of the HSG seeds, and of the composite buffer layer of undoped and lightly doped amorphous silicon layers. A second anneal cycle then allows dopant from the underlying heavily doped amorphous silicon layer to reach the undoped HSG silicon layer, resulting in a doped HSG silicon layer. Patterning, or CMP, of the doped HSG silicon layer, and of the heavily doped amorphous silicon layer, results in the creation of a storage node electrode. The use of the composite buffer layer allows the growth of an undoped HSG silicon layer to be achieved, thus maximizing uniformity and HSG silicon roughness, while the anneal cycle, applied to the undoped HSG silicon layer, results in the attainment of the doped HSG silicon layer, offering reduced capacitance depletion compared to undoped HSG silicon counterparts.