The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2000
Filed:
Jun. 17, 1998
Kuo-Tung Sung, Hsinchu, TW;
Huoy-Jong Wu, Taichung, TW;
Mosel Vitelic, Inc., Hsinchu, TW;
Abstract
A single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate (32) is electrically connected to a PMOS floating gate (34). Both gates are fabricated in a single polysilicon process and form a flash memory cell. The floating gates are programmed by Vcc to the source (14) and drain (26) of the NMOS device (28), while applying about -Vcc to the source (20) of the PMOS device (30). Band-to-band hot electrons charge the floating gates. Biasing the NMOS device to operate as a FET allows the charge state of the gate to be sensed from the source current drawn. The memory cell is erased by applying a moderately high voltage to the source (14) NMOS device while negatively biasing the drain (22) of the PMOS device. In a particular embodiment, an integrated circuit device includes a CMOS circuit and a single-poly flash memory circuit. In a further embodiment, a DC-DC on-chip voltage converter produces the erase voltage from conventional CMOS voltage supplies.