The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2000

Filed:

Mar. 19, 1999
Applicant:
Inventors:

Toshiki Rai, Gifu-ken, JP;

Sadao Yoshikawa, Gifu-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
3651852 ; 3651852 ; 36518521 ; 3651851 ; 36518518 ; 36518525 ;
Abstract

A non-volatile semiconductor memory device including a memory cell transistor, a bit line connected to the memory cell transistor, a current controlling element connected between the bit line and a first potential, a dummy cell transistor connected between the bit line and a second potential, and a decoder connected to the memory cell transistor and the dummy cell transistor. The memory cell transistor has an electrically isolated floating gate electrode which varies an on resistance that depends on an amount of charge stored on the floating gate electrode. The decoder, which controls the memory cell transistor and the dummy cell transistor, is operative during a first interval to turn the dummy cell transistor on to apply the second potential to the bit line which is connected to the first potential via said current controlling element and it is operative during a second interval to turn the memory cell transistor on to allow the second potential to be applied to the bit line via the memory cell transistor, thereby allowing a write-in current to pass via the memory cell transistor.


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