The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2000

Filed:

Nov. 02, 1998
Applicant:
Inventors:

Hao-Chieh Liu, Taipei, TW;

Fu-Liang Yang, Tainan, TW;

Wan-Yih Lien, Hsinchu, TW;

Tzu-Shih Yen, Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438253 ; 438250 ; 438393 ; 438398 ; 438672 ;
Abstract

A process for simultaneously forming storage node structures, for a DRAM cell, and an interconnect structure, for a peripheral region of a DRAM chip, has been developed. The process features the use of dual damascene procedures, with the first damascene procedure used to create the storage node, and interconnect structures, followed by a second damascene procedure, used to create plug structures, used to contact the underlying storage node and interconnect structures. This invention also features the use of SAC openings, allowing the formation of the SAC storage node structures to be realized.


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