The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 07, 2000
Filed:
Nov. 12, 1997
Applicant:
Inventors:
Jian-hui Huang, Mountain View, CA (US);
Ralph Portillo, Mountain View, CA (US);
Fredrick R Gruner, Palo Alto, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
326 39 ; 326 44 ; 326 49 ;
Abstract
The present invention provides a PLA structure having logic interposed between an AND plane and an OR plane, wherein the interposed logic provides an additional set of minterms to the OR plane such that any PLA output function can be implemented with substantially fewer input signals. In this way, parasitic loading for implementation of any particular logic function is reduced.
Quick Actions:
Huang, Jian-hui. (2000). Programmable logic array structure having reduced parasitic loading (U.S. Patent No. 6034543). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6034543
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