Semiconductor memory device having memory cells similarly layouted and

Abstract

A semiconductor dynamic random access memory device includes plural memory cell arrays arranged in two columns, and the memory cell arrays of one column has memory cell sub-arrays and peripheral circuits such as sense amplifiers and sub-word line drivers arranged around the memory cell sub-arrays; the memory cells of the sub-arrays are arranged in a first pattern, and the peripheral circuits of adjacent sub-arrays are arranged in symmetry with respect to a line of symmetry perpendicular to the direction of the columns so as to increase a margin of alignment without sacrifice of simplicity of design work.