The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 29, 2000
Filed:
Dec. 29, 1997
Noriyuki Masuda, Ageo, JP;
Masatoshi Sato, Gyoda, JP;
Advantest Corp., Tokyo, JP;
Abstract
A timing edge forming circuit includes a pattern generator for generating address data, a rate signal and pattern data, a first logic delay circuit for generating first delay time data by the address data wherein the first delay time data includes a first multiple delay time which is an integer multiple of one cycle of the clock signal and a first fractional delay time which is smaller than one cycle of the clock signal, and for sending an enable signal in synchronism with the clock signal which is delayed by the first multiple delay time and the first fractional delay time, a logic delay control circuit for adding the first fractional delay time to skew data to form second delay time data, a second logic delay circuit for providing a second multiple delay time in the second delay time data which is an integer multiple of one cycle of the clock signal to the enable signal, and for producing a second fractional delay time which is smaller than one cycle of the clock signal, a variable delay circuits for providing a high resolution delay time to the delayed enable signal based on the second fractional delay time.