Method for stress testing the memory cell oxide of a dram capacitor

Abstract

A method of stress testing a DRAM such that higher voltages of up to the supply voltage VDD may be applied to the oxide of memory cell capacitors. The DRAM is driven into a stress test mode when the sense amplifiers have been isolated, the precharge voltage and the half bitlines have been grounded, and the word line boost circuitry has been disabled or set to operate at a lower voltage level. These conditions allow the memory cell capacitors, isolated from the sense amplifiers and the word line boost circuitry, to be stress tested independently at a lower power supply and word line voltage levels than are used to stress test conventional DRAMs. The memory cell oxide stresses are applied at room temperature, in wafer form, in seconds instead of hours, and before the configuration of redundancy elements. The inventive method permits the critical burn-in VDD value to be chosen so as to optimize burn-in of the memory cell capacitors and peripheral CMOS circuitry.