Ferroelectric memory device having compact memory cell array

Abstract

A ferroelectric random access memory (FeRAM) is disclosed. The FeRAM (400) provides a folded bit line array having memory cells (402a-402f and 404a-404d) with an area equivalent to 6F.sup.2, where F is a minimum feature size. Reduced array size is achieved by utilizing access transistors of complementary conductivity type within the array. First type memory cells (402a-402f) having n-channel access transistors (N400a-N400f), are formed next to second type memory cells (404a-404d) having p-channel access transistors (P400a-P400d). Bit lines (410a-410e) are arranged into bit line pairs, with a first bit line of each pair being coupled to first type memory cells (402a-402f) and the second bit line of each bit line pair being coupled to second type memory cells (404a-404d). When a word line is driven to a first voltage, ferroelectric capacitor data is driven on the first bit line, while the second bit line provides a reference voltage. When a word line is driven to a second voltage, ferroelectric capacitor data is driven on the second bit line and the first bit line provides a reference voltage.