The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2000
Filed:
Sep. 10, 1998
George Wong, Singapore, SG;
Chartered Semiconductor Manufacturing, Ltd., Singapore, SG;
Abstract
A process for fabricating pixels and bonding pads wherein each has an optimal metal thickness in the fabrication of a LCD integrated circuit device is achieved. Semiconductor device structures are formed in and on a semiconductor substrate wherein the semiconductor device structures are covered by an insulating layer. A first metal layer is deposited overlying the insulating layer and patterned to form a metal line and a bonding pad. A dielectric layer is deposited overlying the metal line and the bonding pad. Vias are opened through the dielectric layer to the metal line but not to the bonding pad. A second metal layer is deposited overlying the dielectric layer and filling the via openings and etched back to form metal plugs. A third metal layer is deposited overlying the dielectric layer and metal plugs and patterned to form pixels contacting metal plugs. A passivation layer is deposited overlying the pixels. A via opening is etched through the passivation layer and the dielectric layer to the bonding pad. A wire bond is formed within the via opening to contact the bonding pad to complete the fabrication of the integrated circuit device.