Multiple row address strobe dram architecture to improve bandwidth

Abstract

A multibank DRAM memory is described having individual row address strobe bar (RASB) and column address strobe bar (CASB) signals. Logically, only one row can be activated in each memory bank at a time and column access can be performed on one memory bank at a time. A token state machine is used to coordinate column access. In a first embodiment, two banks are utilized having respective asynchronous RASB signals transmitted from an external source. In a second embodiment, N DRAM memory banks are utilized having respective asynchronous internal RASB (IRASB) and internal CASB (ICASB) signals. A global RASB signal and a RASB identifier signal (RID) is used to generate the N IRASB and ICASB signals. The RID signal identifies a particular IRASB signal that is to be generated. The token state machine is operated in a round robin manner. In a third embodiment, the N DRAM memory banks are operated in a synchronous manner. The operation of the DRAM memory in this manner overlaps the precharge period associated with accessing one bank with the concurrent access of another bank.