Semiconductor memory array partitioned into memory blocks and sub-blocks

Abstract

A memory circuit that reduces memory operation access time and stress on the memory cells due to memory operations. The memory circuit comprises a semiconductor memory array having a continuously addressable memory space being divided into a plurality of memory array blocks; a memory addressing circuit capable of addressing said continuously addressable memory space of said semiconductor memory array; a memory operation circuit for performing a memory operation on a selected memory cell within a selected memory array block among said plurality of memory array blocks; and a switching network responsive to said memory addressing circuit for selectively coupling said memory operation circuit to said selected memory cell of said selected memory array block by way of said conductive lines, for performing said memory operation on said selected memory cell. A method of addressing and performing memory operations on the memory circuit is also provided herein, that includes the steps of addressing a selected memory array block among said plurality of memory array blocks; addressing a selected memory cell within said selected memory array block; performing a memory operation on said selected memory cell; and isolating at least one unselected memory array block from said step of performing said memory operation on said selected memory cell.