Fast reprogrammable logic with active links between cells

Abstract

A high speed active link switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed. An advantage of the active link technology disclosed herein is that the active links do not degrade rise and fall times of high speed data signals nearly as much as the passive links of prior art field programmable gate arrays thereby enabling use of FPGAs in higher speed applications than was previously possible.