The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2000
Filed:
Dec. 22, 1997
Applicant:
Inventors:
Pidugu L Narayana, Santa Clara, CA (US);
Daniel E Cress, Starkville, MS (US);
Andrew L Hawkins, San Jose, CA (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365203 ; 365233 ;
Abstract
A circuit and method for staggering a bitline precharge between particular sections of a memory array. The present invention may be implemented in memories having increasing depths to reduce unacceptably high precharge current requirements associated with high bitline loads. Since the particular memory sections of the memory array are turned on independently, the peak current necessary to charge the particular bitlines is limited. The present invention may be implemented in logic and may therefore be less sensitive to process and temperature variations.