The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2000
Filed:
Jul. 31, 1998
Sung Soo Cho, Sunnyvale, CA (US);
Nima Homayoun, San Jose, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for stopping a bus clock when there are no activities present on a bus. In the illustrated embodiment, an AGP bus couples a graphics controller to core logic to transfer data between the two devices. A controller generates a first (AGP bus) clock signal CLK and a second (internal) clock signal iclk for the first and second devices. If the controller determines that there are no graphics activities on the AGP bus (i.e., the bus is idle), the controller issues a stop request to stop the internal clock signal iclk. The processing of the stop request is delayed for a period of seven cycles on the AGP bus clock CLK to await for an objection from either the graphics controller or the core logic. If an objection is received during the seven cycle delay, the internal clock iclk will not be stopped, and will continue to run. However, if an objection is not received, then the internal clock iclk will stop. If the graphics controller is in a low power or 'sleep' state, the AGP bus clock CLK is stopped, thereby conserving power.