Semiconductor memory device and method relieving defect of semiconductor

Abstract

A semiconductor memory device includes bit lines and word lines arranged lengthwise and breadthwise, memory cells 1 capable of reading out and writing in, MOS transistors Q1 and Q2 for pre-charge, MOS transistors Q3 for short-circuiting, and transistors Q4 and Q5 for setting voltage level. The bit lines are provided two pieces at each bit. Between the MOS transistors Q1, Q2 for pre-charge and the bit lines driving power supply terminal Vcc, three pieces of the fuses F1-F3 are connected at each column. When the leak defect occurs to the bit lines, all of the fuses F1-F3 connected to the bit lines are cut. Further, a semiconductor memory device includes a plurality of section regions, a redundancy circuit RD1 which replaces a defective cell at each section region, a redundancy circuit RD2 which replaces the defective cell at each row address. The section regions are provided at each address in the column direction. In each section region, cell ground power supply lines Vss are formed circularly. Outside each section region a pad ground power supply line Vss' are formed. Each of the cell ground power supply lines Vss and the pad ground power supply line Vss' are connected via a plurality of fuses F connected in parallel.