The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2000

Filed:

Dec. 29, 1997
Applicant:
Inventors:

Seiichi Shishiguchi, Tokyo, JP;

Tomoko Yasunaga, Tokyo, JP;

Akira Mineji, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
438696 ; 438230 ; 438595 ; 438703 ; 438683 ;
Abstract

The present invention provides a method of forming gate side wall insulation films on side walls of a gate electrode on a gate insulation film over a silicon substrate surface. The method comprises The following steps. Gate side wall insulation films are selectively formed on side walls of a gate electrode. A silicon film is selectively grown on at least any one of a top of the gate electrode and on the silicon substrate surface. Surface regions of the gate side wall insulation films are etched.


Find Patent Forward Citations

Shishiguchi, Seiichi. (2000). Method of forming a mos field effect transistor with improved gate side (U.S. Patent No. 6017823). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6017823

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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