The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2000

Filed:

Feb. 26, 1998
Applicant:
Inventors:

Katsuhiko Hieda, Yokohama, JP;

Tsunetoshi Arikado, Tokyo, JP;

Katsuya Okumura, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257310 ; 257295 ; 257301 ;
Abstract

A semiconductor memory device comprises a matrix of memory cells, each having a transistor and a capacitor. A first electrode, a dielectric film and a second electrode are sequentially staked on a silicon monocrystalline substrate and epitaxially grown to form a capacitor having a multilayer structure. Then, an SOI layer is formed on the monocrystalline substrate carrying thereon the capacitor with an insulator film interposed therebetween. A source/drain diffusion layer is formed in the SOI layer and a gate electrode is formed to produce a MOS transistor. Either the source or the drain of the source/drain diffusion layer of the transistor is connected to the second electrode by way of the polysilicon layer in the contact hole running through the SOI layer and the insulator film layer.


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