The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2000
Filed:
Mar. 24, 1998
Wataru Igarashi, Yokohama, JP;
Yasuo Naruke, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A semiconductor device comprises: a semiconductor substrate; a field oxide film formed in the semiconductor substrate, the field oxide film having element forming regions on both sides thereof; a pair of MOS transistors formed in the element forming regions on both sides of the field oxide film, each of the transistors having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate, the field oxide film and the transistors; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, the first opening being arranged above the field oxide film and having a greater width than the field oxide film, an inner one of the pair of source/drain regions of each of the pair of transistors being exposed to the first opening, the inner one of the pair of source/drain regions of one of the pair of transistors being electrically connected to the inner one of the pair of source/drain regions of the other of the pair of transistors by means of the local interconnect; and a pair of buried contacts formed by embedding a pair of conductive materials in a pair of second openings formed in the interlayer insulating film, the pair of second openings being arranged above an outer one of the pair of source/drain regions of each of the pair of transistors, the outer one of the pair of source/drain regions being exposed to the second openings.