The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2000

Filed:

May. 26, 1999
Applicant:
Inventors:

Rong-Wu Chien, Hsin-Chu, TW;

Hsiao-Chiu Tuan, Hsin-Chu, TW;

Chao-Ming Koh, Hsin-Chu, TW;

Tung Chia Ching, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438396 ; 438398 ; 438255 ;
Abstract

A process for forming a DRAM capacitor structure, comprised with a HSG silicon/polysilicon crown shaped storage node structure, has been developed. The process features the use of a series of wet clean procedures, used to prepare the surface of the HSG silicon/polysilicon, crown shaped storage node structure, for the formation of an overlying capacitor dielectric layer. A first wet clean procedure is employed after the formation of the crown shaped storage node structure via a CMP procedure, featuring an ammonium hydroxide--hydrogen peroxide solution, used to remove CMP, as well as HSG silicon particles from the surface of a photoresist plug used for definition of the crown shaped storage node structure. Another wet clean procedure, first performed in a DHF solution, then followed by a sulfuric acid--hydrogen peroxide treatment, is used to prepare the HSG silicon/polysilicon, crown shaped storage node structure, for formation of the overlying capacitor dielectric layer.


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