The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2000
Filed:
Mar. 02, 1998
Shou-Wei Hsieh, Hsinchu, TW;
Utek Semiconductor, Corp., Hsinchu, TW;
Abstract
A method of making dual-gate structure with only three masking steps is provided. The process comprising: forming well and isolation region to define PMOS and NMOS regions on a semiconductor substrate; forming a conformal layer of PMOS gate oxide by thermal oxidation; providing a conformal layer of P type conducting material overall; removing portions of the P type material and PMOS gate oxide on the NMOS region with the aid of the first patterned mask; forming a conformal layer of NMOS gate oxide by thermal oxidation; providing a conformal layer of N type conducting material overall; forming the NMOS gate structure with the aid of the second patterned mask; performing ion implantation; providing a conformal layer of oxide overall, then etching into NMOS spacers; performing ion implantation; providing a conformal layer of protecting dielectric layer overall; proving the third patterned mask to remove portions of the protecting dielectric layer, the NMOS gate oxide, P type conducting layer and PMOS gate oxide to form the PMOS gate structure, thereby leaving a protecting dielectric layer over the NMOS region; performing ion implantation; providing a conformal layer of oxide overall, then etching into PMOS spacers; performing ion implantation.