The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 1999
Filed:
May. 30, 1997
Koichi Sato, Tokyo, JP;
Hideyuki Emura, Tokyo, JP;
Naotaka Maeda, Tokyo, JP;
Masamichi Kawarabayashi, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A delay optimization system including a layout processing unit for receiving the input of circuit specification of a target circuit to conduct layout, as well as extracting wiring information, an optimization processing unit for conducting optimization with reference to the wiring information, as well as generating circuit change information and inserted buffer information, and a constraints violations determining unit for determining whether a circuit generated as a result of the layout by the layout processing unit satisfies delay constraints set for the target circuit, the layout processing unit executing initial layout based only on circuit information synthesized based on the circuit specification of the target circuit and re-layout with reference to the circuit change information and inserted buffer information generated by the optimization processing unit.