The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 1999
Filed:
Jun. 23, 1997
Atila Mertol, Cupertino, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate and a heat spreader. The chip includes multiple I/O pads preferably arranged in a two-dimensional array on an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The substrate maintains its substantially planar shape during C4 heating. The heat spreader is thermally conductive and preferably dimensioned to substantially cover the upper surface of the substrate. An underside surface of the heat spreader includes a cavity dimensioned to receive the chip and multiple pins extending outwardly therefrom. The substrate includes multiple holes adapted to receive the pins of the heat spreader. Following the C4 mounting of the chip upon the substrate, the heat spreader is attached to the upper surface of the substrate such that the pins of the heat spreader extend into the holes of the substrate and the chip resides within the heat spreader cavity. The ends of the heat spreader pins are connected to at least one member of a second set of bonding pads on the underside surface of the substrate, providing additional thermal paths for the dissipation of heat energy produced by the chip during operation.