The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 1999
Filed:
Jun. 18, 1998
Kenji Ueda, Osaka, JP;
Kyoko Egashira, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A method for fabricating a semiconductor memory device such as an EEPROM including, in a semiconductor substrate having a first conductivity type, forming a source region and a drain region having a second conductivity type opposite to the first conductivity type. A trench having a prescribed thickness from a main surface of said semiconductor substrate toward inside thereof is formed in an area to be an element isolation region of the semiconductor substrate. A remaining portion of the semiconductor substrate defines an element forming region. Embedding an element isolation insulating film in the trench to substantially fill the trench. A first insulating film is formed on the element forming region and on at least a portion of the element isolation insulating film. A floating gate electrode is formed on the first insulating film, a second insulating film is formed on the floating gate electrode, a control gate electrode is formed on the second insulating film, a third insulating film to be a tunneling medium is formed on a side of the floating gate electrode, and an erasing gate electrode is formed so as to cover said third insulating film.