The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1999
Filed:
May. 27, 1999
Hsiao-Ying Yang, Hsin-Chu, TW;
Yeh-Sen Lin, Tao-Yuan, TW;
Vanguard International Semiconductor Corporation, Hsin-Chu, TW;
Abstract
A process for fabricating a straight walled, silicon nitride capped, gate structure, for a MOSFET device, has been developed. The process features the creation of a straight walled, photoresist shape, to be used as an etch mask, during the patterning of the straight walled, silicon nitride capped, gate structure. A silicon oxynitride layer, with a specific thickness range between about 820 to 920 Angstroms, is used as a bottom anti-reflective coating, (BARC), layer, located between an overlying straight walled, photoresist shape, and an underlying silicon nitride capping layer. The BARC layer retards the reflection emitted from a silicon nitride capping layer, during the photolithographic exposure procedure, used for definition of the straight walled, photoresist shape, allowing the desired straight walled, photoresist shape, to be obtained, independent of the thickness of the silicon nitride capping layer. The ability to fabricate straight walled, silicon nitride capped, gate structures, allows control, and uniformity, of channel regions, located underlying the straight walled, silicon nitride capped, gate structure, and between source/drain regions, self-aligned to the straight walled, silicon nitride capped, gate structures, to be realized.