The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1999
Filed:
Feb. 20, 1997
Yoshihiro Hayashi, Tokyo, JP;
Nobuhiro Tanabe, Tokyo, JP;
Tsuneo Takeuchi, Tokyo, JP;
Shinobu Saito, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
In a method of manufacturing a semiconductor device, a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor is formed on a substrate. A plurality of conductive plugs is formed to penetrate a laminate insulating film to the MOS transistors. The laminate insulating film is composed of a first insulating film and a second insulating film. A capacitor section is formed on the laminate insulating film and the capacitor section is composed of an upper electrode, a dielectric film and a lower electrode. A third insulating film is formed on the laminate insulating film and the capacitor section. A wiring pattern is formed on the third insulating film to partially penetrate the second insulating film connect to the plurality of conductive plugs. A wiring pattern may be disposed in the laminate insulating film to connect at least two of the plurality of conductive plugs.