Method of manufacturing a triple level rom

Abstract

A method of making a triple level ROM device includes forming at least first, second and third metallic oxide semiconductor (MOS) structures. Each MOS structure has a source terminal and a drain terminal located within a substrate, a channel located between the source and drain terminals, and a gate terminal structure located above the channel. The source and drain terminals serve as bit lines and the gate terminal serves as a word line. A dielectric layer and a cap layer are formed in sequence above the first, second and third MOS structures, thereby forming first, second and third memory cell units from the first, second and third MOS structures, respectively. A first coding process is performed, which includes forming a photoresist layer above the gate terminal structure of at least the first memory cell unit. Portions of the cap layer having no photoresist coverage are removed to form a cap above the first memory cell unit. A second coding process is performed, which includes selectively implanting ions into the channel regions of the first and second memory cell units, whereby threshold voltages of the first and second memory cell units, respectively, are adjusted. The invention is also directed to a triple level ROM structure including a plurality of metallic oxide semiconductor memory cell units, which include source/drain regions, channel regions having impurity concentrations different from each other, gate terminal structures, and caps located over the gate terminal structures.